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1

[IEEE 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Lubeck, Germany (2007.08.29-2007.08.31)] 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) - Test Controller Synthesis Constrained by Circuit Testability Analysis

Ruzicka, Richard, Strnadel, Josef

Year:

2007

Language:

english

File:

PDF, 340 KB

english, 2007

2

Predictability Analysis of Interruptible Systems by Statistical Model Checking

Strnadel, Josef

Journal:

IEEE Design and Test

Year:

2018

Language:

english

File:

PDF, 800 KB

english, 2018

3

[IEEE 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Florence, Italy (2019.3.25-2019.3.29)] 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates

Strnadel, Josef

Year:

2019

Language:

english

File:

PDF, 184 KB

english, 2019

4

[IEEE 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Tallinn, Estonia (2012.04.18-2012.04.20)] 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) - Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systems

Strnadel, Josef

Year:

2012

Language:

english

File:

PDF, 207 KB

english, 2012

5

[IEEE 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Vienna, Austria (2010.04.14-2010.04.16)] 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems - Reduction of power dissipation through parallel optimization of test vector and scan register sequences

Kotasek, Zdenek, Skarvada, Jaroslav, Strnadel, Josef

Year:

2010

Language:

english

File:

PDF, 326 KB

english, 2010

6

[IEEE 2011 14th Euromicro Conference on Digital System Design (DSD) - Oulu, Finland (2011.08.31-2011.09.2)] 2011 14th Euromicro Conference on Digital System Design - On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits

Rumplik, Michal, Strnadel, Josef

Year:

2011

Language:

english

File:

PDF, 497 KB

english, 2011

7

[IEEE 2014 17th Euromicro Conference on Digital System Design (DSD) - Verona, Italy (2014.8.27-2014.8.29)] 2014 17th Euromicro Conference on Digital System Design - Comparing Availability-Aware Real-Time Schedulers by Means of Configurable Experimental Framework

Strnadel, Josef, Pokorny, Martin

Year:

2014

Language:

english

File:

PDF, 296 KB

english, 2014

8

[IEEE 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD) - Lille, France (2010.09.1-2010.09.3)] 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools - The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption

Kotasek, Zdenek, karvada, Jaroslav, Strnadel, Josef

Year:

2010

Language:

english

File:

PDF, 420 KB

english, 2010

9

[IEEE 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - Parma, Italy (2008.09.3-2008.09.5)] 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools - TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path

Strnadel, Josef

Year:

2008

Language:

english

File:

PDF, 434 KB

english, 2008

10

[IEEE 2012 15th Euromicro Conference on Digital System Design (DSD) - Cesme, Izmir, Turkey (2012.09.5-2012.09.8)] 2012 15th Euromicro Conference on Digital System Design - On Distribution and Impact of Fault Effects at Real-Time Kernel and Application Levels

Strnadel, Josef, Slimarik, Frantiek

Year:

2012

Language:

english

File:

PDF, 347 KB

english, 2012

11

[IEEE 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems (ECBS-EERC) - Brno, Czech Republic (2015.8.27-2015.8.28)] 2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems - Comparison of Generally Applicable Mechanisms for Preventing Embedded Event-Driven Real-Time Systems from Interrupt Overloads

Strnadel, Josef

Year:

2015

Language:

english

File:

PDF, 297 KB

english, 2015

12

[IEEE 2016 Austrochip Workshop on Microelectronics (Austrochip) - Villach, Austria (2016.10.19-2016.10.19)] 2016 Austrochip Workshop on Microelectronics (Austrochip) - On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

Strnadel, Josef, Risa, Michal

Year:

2016

Language:

english

File:

PDF, 1.71 MB

english, 2016

13

Nested Loops Degree Impact on RTL Digital Circuit Testability 1

Strnadel, Josef

Journal:

IFAC Proceedings Volumes

Year:

2003

Language:

english

File:

PDF, 544 KB

english, 2003

14

[IEEE 2017 Euromicro Conference on Digital System Design (DSD) - Vienna, Austria (2017.8.30-2017.9.1)] 2017 Euromicro Conference on Digital System Design (DSD) - On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model Checking

Strnadel, Josef

Year:

2017

Language:

english

File:

PDF, 352 KB

english, 2017

15

[IEEE 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Florence, Italy (2019.3.25-2019.3.29)] 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) - Using Statistical Model Checking to Assess Reliability for Bathtub-Shaped Failure Rates

Strnadel, Josef

Year:

2019

File:

PDF, 184 KB

2019

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